Cadence SPB Allegro and OrCAD 17.40.000-2019 HF014

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Cadence SPB Allegro and OrCAD 17.40.000-2019 HF014 | 5.6 Gb
Cadence Design Systems, Inc. , the leader in global electronic design innovation, has unveiled a new of improvements in hotfix 014 to the Cadence SPB Allegro and OrCAD 17.40 families of products aimed at boosting performance and productivity through improvements features and big fixed issues.

CCRID Product ProductLevel2 Title

2364495 ADW COMPONENT_BRO DE-HDL Part Manager - Part Table Filter window issue in release 17.4-2019: Window is shifted up and is not fully visible
2361104 ADW DBEDITOR Schematic model losing association to the part number in Database Editor
2324712 ALLEGRO_EDITOR 3D_CANVAS Incorrect component placement after bending in 3D Canvas
2331953 ALLEGRO_EDITOR 3D_CANVAS Finished hole size conflict: Difference in measurement of diameter in 3D Canvas
2351250 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas Collision Detection segmentation fault
2427277 ALLEGRO_EDITOR 3D_CANVAS Conflict in finished hole size in 3D Canvas and 2D.
2428041 ALLEGRO_EDITOR 3D_CANVAS Hole plating is displayed incorrectly for 3D Canvas
2342729 ALLEGRO_EDITOR CROSS_SECTION Total thickness and other values in the 'Info' section of Cross-section Editor do not change in Multi Stackup Mode
2346225 ALLEGRO_EDITOR CROSS_SECTION Release 17.4-2019: Cross-section not showing correct thicknesses of different zones
2366440 ALLEGRO_EDITOR CROSS_SECTION Info tab of Cross-section Editor not showing thickness of the selected stackup
1984203 ALLEGRO_EDITOR DATABASE Drill holes not displayed correctly in the Zone area
2338909 ALLEGRO_EDITOR DFM Pin to Line Same Net Spacing, DFF spacing not Flagged DRC
2353416 ALLEGRO_EDITOR DFM Cannot add comment when waiving a DRC in release 17.4-2019, but was allowed in release 17.2-2016
2416910 ALLEGRO_EDITOR DFM DFF bug about cutout to shape spacing: DRC not shown if part of shape inside cutout
2408246 ALLEGRO_EDITOR GRAPHICS GPU acceleration: Radius corners on padstacks are inverted on move
2421922 ALLEGRO_EDITOR INTERFACES PDF Export does not honor colors on hatched shapes
2364660 ALLEGRO_EDITOR MCAD_COLLAB Importing IDX in Allegro PCB Editor does not import the correct drill size and plating type.
2330770 ALLEGRO_EDITOR PLACEMENT Allegro PCB component placed outside of drawing extents; symbol does not fit into the drawing
2415259 ALLEGRO_EDITOR REPORTS Allegro PCB Editor stops responding on running DRC Report from Status dialog DRC button when DRC count is very high
2348624 ALLEGRO_EDITOR SCHEM_FTB Design Sync removing Mounting Holes
2210611 ALLEGRO_EDITOR SHAPE Void in Shape for Unused Embedded Component Pins
2332910 ALLEGRO_EDITOR SHAPE Unintended voids on Layers for indirect attach via
2342975 ALLEGRO_EDITOR SHAPE PolyBool is running out of memory with arc during poly-operation called from SKILL
2359333 ALLEGRO_EDITOR SHAPE Pads missing thermals in release 17.2-2016
2422586 ALLEGRO_EDITOR SHAPE Shape partially disabled when using QIR2, shape fast mode
2360393 ALLEGRO_EDITOR THIEVING Information missing for error code SPMHMF-199: No thieving shape is left after voiding.
2344693 ALLEGRO_EDITOR UI_GENERAL Command window loses focus for keyboard commands or aliases
2345533 ALLEGRO_EDITOR UI_GENERAL 'show element' stops responding if run on many objects
2351789 ALLEGRO_EDITOR UI_GENERAL Fail to open Allegro Package Designer Plus, Allegro PCB Editor, and any other applications in Linux SUSE12
2364030 ALLEGRO_EDITOR UI_GENERAL Setting variable and using a template board still opens the new design form.
2369265 ALLEGRO_EDITOR UI_GENERAL Allegro PCB Editor crashes on running 'prepopup' command
2399078 ALLEGRO_EDITOR UI_GENERAL Floating 'Visibility', 'Find', and 'Options' panes are visible when running Allegro PCB Editor with '-nograph'
2399253 ALLEGRO_EDITOR UI_GENERAL axlFormGridSetSelectRows() is not selecting rows in release 17.4-2019, but works in release 17.2-2016.
2289044 ALLEGRO_LIB_CRT CORE Scrolling changes list properties in Properties Terminal window
2291932 ALLEGRO_LIB_CRT CORE LC does not load changed footprints
2311602 ALLEGRO_LIB_CRT CORE Unable to change some Advanced Settings: Can be changed using XML but not from GUI
2322838 ALLEGRO_LIB_CRT CORE LC - View Footprint shows incorrect paste mask
2352074 ALLEGRO_LIB_CRT CORE Need to log in twice into LC repository: Authorization error on first try
2354152 ALLEGRO_LIB_CRT CORE Release 17.4-2019, LC crashes when editing padstack
2354159 ALLEGRO_LIB_CRT CORE Release 17.4-2019, LC creates wrong contact area
2415073 APD DIE_GENERATOR Problem importing die text file: Allegro Package Designer Plus stops responding
2428118 APD DIE_STACK_EDI Allegro Package Designer Plus closes on attempting to open die stack editor
2354812 APD VIA_STRUCTURE Loading via structure after removing all instances results in error (SPMHII-507) related to symbol definition
2412221 APD WIREBOND When moving Tack Points using Auto Spread the tool will lock up
2374740 CAPTURE NETLISTS Capture is crashing during create netlist with design
2328262 CAPTURE OTHER Localize Part Manager menu for Japanese
2330271 CAPTURE OTHER Release 17.4-2019: Capture crashes when design opened from server
2332901 CAPTURE OTHER Save Project As command creates multiple folders if folder name has acute accent mark (á)
2307691 CIS PART_MANAGER Capture CIS stops responding on linking database part from Part Manager
2340055 CIS PART_MANAGER Capture and CIS Explorer stop responding if Part Manager is not opened before CIS Explorer
2354106 CONCEPT_HDL COPY_PROJECT Release 17.4-2019: Copy Project does not preserve module_order.dat
2309487 CONCEPT_HDL CORE Running script with 'no_graphic' does not minimize GUI
2340900 CONCEPT_HDL CORE Release 17.4-2019: Choosing 'Help->About' crashes Design Entry HDL
2347561 CONCEPT_HDL CORE DE-HDL Windows mode selection allows unintentional moving of objects
2350410 CONCEPT_HDL CORE DE-HDL 'Rename Signal' behaving inconsistently: Net needs to be selected and cursor placed before choosing option
2357604 CONCEPT_HDL GLOBALCHANGE Global modify GUI fields are cropped
2312845 CONSTRAINT_MGR ANALYSIS Release 17.4 Allegro Physical Viewer Plus: 'Analyze' option missing from pop-up menu
2363853 CONSTRAINT_MGR CONCEPT_HDL Release 17.4-2019 DE-HDL CM Class to Class Spacing Constraint name incorrect when Class name GND used
2327886 CONSTRAINT_MGR OTHER Licensing issue with OrCAD PCB Designer Standard and Static Phase at Vias option
2346012 CONSTRAINT_MGR TECHFILE Interlayer Spacing checks is not active after importing techfile
2288948 CONSTRAINT_MGR UI_FORMS Change Save icon to a floppy disc to match other schematic editors
2341693 CONSTRAINT_MGR UI_FORMS Release 17.4-2019, Constraint Manager: Need ability to change icons
2341421 F2B DESIGNVARI Variant management of custom variables upon variants copy: Defaults to base value
2360447 GRE IFP_INTERACTI Cannot blank bundled rats after doing 'Display - Show Rats - Net'
2335847 PCB_LIBRARIAN SYMBOL_EDITOR Error notification when launching Symbol Editor with locked grid settings
2356726 PCB_LIBRARIAN SYMBOL_EDITOR Symbol_Units LOCK directive pop-up messages when cell opened in PDV
2317881 PCB_LIBRARIAN SYMBOL_EDITOR Cannot change grid visibility using 'eye' icon in new Symbol Editor
2320117 PSPICE MODELEDITOR Menu of Model Editor cannot be localized.
2270037 PSPICE MODELING_APPS Cannot edit PSpice center tap transformer component after placing it
2294168 PSPICE SIMULATOR Strange result if PWL sources are used
2312121 PSPICE SIMULATOR ETable function does not support values defined as parameters
2313080 PSPICE SIMULATOR Cannot define parameters for ETable
2333346 PSPICE TI_CONTRACT Constrained Manager related dictionary not found error on running PSpice for TI
2364119 PULSE ADHOC Error VOS-31 should clear itself when resolved
2421385 PULSE ADHOC Copied project maintains the version history of the source and is not seeing commits to this project
2364115 PULSE CORE LiveBOM and PDF data not getting generated in master/data setup
2400092 PULSE R2PLM-WC PFM stops responding during publishing when WC EPM doc numbers are auto-created with spaces
2416512 SIP_LAYOUT STREAM_IF Some arcs go to the wrong direction in GDS in release 17.4-2019
2417082 SIP_LAYOUT STREAM_IF Some arcs go to the wrong direction in GDS in release 17.2-2016, HotFix 072
2401836 SPIF OTHER Allegro PCB Editor crashes on exporting to Allegro PCB Router or running 'auto_route'
2409784 SYSTEM_CAPTURE CONTEXT_MENUS Tcl scripting - Adding context menu to a component not working
2363049 SYSTEM_CAPTURE HIERARCHY Allegro System Capture shows two times the number of blocks in schematic in the design hierarchy
2411591 SYSTEM_CAPTURE IMPORT_DEHDL_ DE-HDL to ASC conversion and exporting netlist to board 100% connected creates opens
2361129 SYSTEM_CAPTURE NETGROUP Allegro System Capture copy and paste signals from netgroups result in renamed signals after pasting when they exist
2274198 SYSTEM_CAPTURE PACKAGER The Assign Pin Number pop-up menu option either does not work or is grayed out
2334299 SYSTEM_CAPTURE SELECTION Selection behaves unexpectedly if a group selection is made followed by selecting a single wire with a net name
2363137 SYSTEM_CAPTURE SYMBOL_GRAPHI Graphics in Symbol Editor do not match what is shown in System Capture.
2321518 SYSTEM_CAPTURE VARIANT_MANAG Defining variants in System Capture: Variant information lost on copy-paste
2412827 SYSTEM_CAPTURE WIRING Crash when connecting to pin 25 of part 0001-0284.955
2301885 TOPXP SSIVIEWER Display results of interest rather than showing all the waveforms in SSIviewer after SSI-PBA simulation

Cadence OrCAD and Allegro 17.4-2019is a sleeker and more modern version of the OrCAD and Allegro release, with enhanced usability and a slew of new productivity- enhancing features. You get more intuitive and easy- to- use flows that enable optimized schematic- to- board- to- manufacturing transitions. So, whether you design schematics, work with physical layouts, manage or create libraries and parts, or administer ECAD processes, there are features in this release that will benefit you.
Starting with OrCAD and Cadence Allegro PCB - Tutorial for Beginners
Cadenceenables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry.
Product:Cadence SPB Allegro and OrCAD
Version:17.40.000-2019 HF014
Supported Architectures:x64
Website Home Page :www.cadence.com
Language:english
System Requirements:PC *
Software Prerequisites:Cadence SPB Allegro and OrCAD 17.40.000-2019 and above
Size:5.6 Gb

System Requirements:
OS:Windows 10 (64-bit) Professional, Windows Server 2012 (All Service Packs); Windows Server 2012 R2; Windows Server 2016.
CPU:Intel Core i7 4.30 GHz or AMD Ryzen 7 4.30 GHz with at least 4 cores
Memory:16 GB RAM
Space:50 GB free disk space (SSD drive is recommended)
Display:1920 x 1200 display resolution with true color (at least 32bit color)
GPU:A dedicated graphics card supporting OpenGL, minimum 2GB (with additional support for DX11 for 3D Canvas)
Monitors:Dual monitors (For physical design)
Supported MATLAB Version:R2019A-64Bit (For the PSpice-MATLAB interface)

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